Qualifications:

-Applicants should possess a Master’s Degree in Electrical Engineering, or a Bachelor’s Degree with at least 5-10 years of applicable experience
-Familiarity with test equipments such as VNA and TDR.
-Knowledge of simulation and layout tools such as HFSS, OrCAD, LTSpice and PSpice
-Knowledge of scripting languages such as MathLab, Perl/TK and Python are plus
-Team leadership is a plus

Responsibilities:

-You will be working with a team of Signal Integrity Engineers to develop the interconnect designs for state-of-the-art test point adapter to support the latest standards such as IEEE802.3, OIF and PCI-SIG.
-Leading and/or coordinating a team of designer engineers, customer teams, etc.
-Electrical modeling and simulation of high speed IO interconnects.
-Definition and evaluation of circuit design features required to support interconnect performance requirements
-Creation of signal measurement test plans and review of measurement results
-Correlation of measurements to simulations, and modification of models as required